The present invention relates generally to semiconductors, and more specifically the invention pertains to a means of testing ohmic contacts on microelectronics.
Metallization films commonly used for interconnecting components on microelectronic devices are subject to a variety of defect and wearout related failure mechanisms. These mechanisms can give misleading results during burn-in testing of semiconductors. Burn-in testing is part of a normal fabrication process and it entails the operation of a device at a higher than normal temperature, voltage level or normal frequency of operation to test for circuit failures. Unfortunately, burn-in testing can be misleading in that defective metal conductors may not fail in the limited burn-in time, and it is not possible to accelerate the failure by increasing current density through the defect. For example, deposition process and patterning problems, as well as foreign particles, may result in areas of extra or missing metal, or reduced film thickness so that the metal contact may fail in a year at normal use conditions, but will not fail in burn-in. Also, metallization microstructure and thermal or mechanical stress and stress gradients in overcoat insulator and metal films may influence or drive mass transport failure mechanisms. Metal atom vacancy diffusion flux divergences may occur at grain boundary triple points, and this is thought to cause observed mass transport, or electromigration, of metal from certain areas to others. These failure mechanisms generally work to shorten the life-time of the conductors in which they occur by causing and/or growing voids or metal protrusions. Voids may reduce the stripe cross-sectional area, increase the current density in it, and in turn cause increased resistance, timing faults, or open circuits. Protrusions may cause shorts between normally isolated stripes.
Ideally, none of the failure mechanisms described above would be present in a particular integrated circuit manufactured with well controlled materials, processes, design rules, and in-use current densities. Ideally, all circuits would be manufactured with predictable lifetime characteristics. In reality, it is very difficult to assure that this is the case, and there is much evidence that these failure mechanisms are not completely understood, modeled, and controlled. Further, there is evidence that there may be synergy among some of these failure mechanisms. Under some conditions the presence or action of one failure mechanism may alter the rate of another. For example, a slit void may grow laterally due to electromigration from the side of a stress relief notch void, causing mechanical stress gradient changes and electrical resistance changes, all the while being influenced by thermal gradients established by current flow in and heat sinking of the stripe. It may be difficult to determine the reliability of a particular part since it may depend on its weak link, which may in turn depend on a number of factors such as photolith flaws, residual built-in mechanical stress, grain boundary orientation, thermal history, and the distribution of stripe lengths in the part. These complexities make metal film reliability modeling, prediction, and assurance difficult and questionable on a part-by-part basis.
The task of testing semiconductors accurately without having a failure in ohmic contacts is alleviated, to some extent, by the systems disclosed in the following U.S. Patents, the disclosures of which are incorporated herein by reference:
U.S. Pat. No. 5,130,644 issued to Ott;
U.S. Pat. No. 5,047,711 issued to Smith et al; and
U.S. Pat. No. 4,760,032 issued to Turner.
The patent to Turner discloses the patterning of an aluminum layer for testing insulating oxide films and the removal of the aluminum layer after testing. The Turner aluminum layer does not allow for high current path testing, and doesn't acknowledge that traditional burn-in testing can be enhanced to screen conductors and contacts. The remaining patents are of interest for other testing approaches.
Several approaches are used in the present art to assure metal film reliability. Process controls, particle and defect reduction measures, and current density design rules attempt to eliminate or control the root causes of the failure mechanisms. Wafer level acceptance tests or fast reliability tests may be used to monitor process outcomes by using special test structures and fast tests. These may measure some parameter related to expected lifetime, and are usually done at very high stress conditions compared to those experienced during use. Scanning electron microscope inspections may be used to inspect step coverage, and void sizes and densities. Functional testing and burn-in of finished parts may be used to weed out those containing failed conductors. However, since these failure mechanisms depend on the local micro structure, tests done on material other than the finished part itself may or may not predict the condition and behavior of the finished part. This is especially true where the failure mechanism is influenced by some factor which is located randomly, or in a manner which cannot be strictly controlled, such as grain boundary size and orientation, or particle deposition.
There are no tests or screens available in the present art which allow evaluation of all of the patterned conductors and contacts in an individual part after deposition, except for functional testing, which uses low current densities limited by the saturated drain currents of transistors, and short periods of time. Functional testing may not cause failure or detection of unreliable conductors, and 100% inspection is not practical now.